Hierarchical structure due to the relationship between physics and costs:
The faster the bus, the shorter it is.
The faster the bus, the more complex it is to design and build (hence more costly).
Modern system architecture
Specialized chipsets and faster point-to-point interconnects.
A Canonical Device
A common abstraction
Conceptual model/template for all I/O devices.
Interface: allowing system software to control the device’s operations
Initialize/configure
Start/stop operation
Check status/handle interrupts
Bridged with OS by device driver.
Internal structure: implementing the abstraction presented to the system.
Controller/firmware
Registers
Buffer memory
Bus interface
Common Abbreviations:
DMI: Direct Memory Interface
ATA: IBM’s PC AT Attachment.
SATA: Serial ATA
eSATA: External Serial ATA
PCIe: Peripheral Component Interconnect Express
A simple canonical protocol
Repeatedly read the register for READY status.
Send data to register (Programmed I/O - PIO).
Write a command to the command register to initiate device execution.
Wait until the device is done.
What is a problem with this approach?
Hardware interrupts
Instead of polling the device, the OS can:
After issue an I/O request, put the calling process to sleep and context switch to another.
When the request is finished, the device will raised a hardware interrupt to return CPU to the OS.
Predetermined interrupt service routine (ISR) - interrupt handler.
This allows overlap of computation and I/O (recall CPU scheduling slides)
To avoid interrupts all the time, a hybrid model is employed (scheduling).
Programmed I/O overheads
Programmed I/O: I/O instructions that move data from storage into register for computation purposed. This requires the CPU’s involvement in every transactions.
With programmed I/O, the CPU spends too much time moving data to and from devices.
How do we offload this work: Direct Memory Access (DMA) device
Orchestrate transfer between devices and main memory without much CPU intervention.