:class: tip
This lecture will cover contents from Chapter 11 of the book.
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## Memory abstraction: writing and reading memory
- Write:
- Transfer data from CPU to memory: `movq 8(%rsp), %rax`
- `Store` operation
- Read:
- Trasnfer data from memory to CPU: `movq %rax, 8(%rbp)`
- `Load` operation
- Physical representation of this abstraction:
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- Key features:
- RAM is traditionally packaged as a chip, or embedded as part of processor chip
- Basic storage unit is normally a cell (one bit per cell).
- Multiple RAM chips form a memory.
- RAM comes in two varieties:
- SRAM (Static RAM): transistors only
- DRAM (Dynamic RAM): transistor and capacitor
- Both are volatile: memory goes away without power.
:::::{tab-set}
::::{tab-item} SRAM/DRAM
:::{list-table}
:header-rows: 1
* -
- SRAM
- DRAM
* - Transitor per bit
- 6 or 8
- 1
* - Access time
- 1x
- 10x
* - Need refressh
- No
- Yes
* - Need EDC
- Maybe
- Yes
* - Cost
- 100x
- 1x
* - Applications
- Cache memories
- Main memories, frame buffers
:::
::::
:::::
*EDC: Error Detection and Correction*
- Trends:
- SRAM scales with semiconductor technology
- Reaching its limits
- DRAM scaling limited by need for minimum capacitance
- Aspect ratio limits how deep can make capacitor
- Also reaching its limits
- Operation of DRAM cell has not changed since its invention
- Commercialized by Intel in 1970.
- DRAM cores with better interface logic and faster I/O :
- Synchronous DRAM (SDRAM)
- Uses a conventional clock signal instead of asynchronous control
- Double data-rate synchronous DRAM (DDR SDRAM)
- Double edge clocking sends two bits per cycle per pin
- Different types distinguished by size of small prefetch buffer:
- DDR (2 bits), DDR2 (4 bits), DDR3 (8 bits), DDR4 (16 bits)
- By 2010, standard for most server and desktop systems
- Intel Core i7 supports DDR3 and DDR4 SDRAM
Temporal locality: Recently referenced items are likely to be referenced again in the near futureSpatial locality: Items with nearby addresses tend to be referenced close together in time
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sum = 0;
for (i = 0; i < n; i++)
sum += a[i];
return sum;
spatial sum each iteration: temporal spatial temporal 
:::::{tab-set}
::::{tab-item} Exercise 1
Does this function have good locality with respect to array a?
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int sum_array_rows(int a[M][N]) {
int i, j, sum = 0;
for (i = 0; i < M; i++)
for (j = 0; j < N; j++)
sum += a[i][j];
return sum;
}
:::{admonition} Answer
Yes
::: ::::
::::{tab-item} Exercise 2
Does this function have good locality with respect to array a?
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int sum_array_rows(int a[M][N]) {
int i, j, sum = 0;
for (j = 0; j < N; j++)
for (i = 0; i < M; i++)
sum += a[i][j];
return sum;
}
:::{admonition} Answer
Yes
:::
:::: :::::
05-memory and change into this directory.sum.c with the following contents::::::{tab-set} ::::{tab-item} Compile and run
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$ gcc -Og -o sum sum.c
$ ./sum
$ ./sum
$ ./sum
$ ./sum
:::: ::::{tab-item} Result
::::
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## Memory hierarchies
- Some fundamental and enduring properties of hardware and software:
- Fast storage technologies cost more per byte, have less capacity,
and require more power (heat!).
- The gap between CPU and main memory speed is widening.
- Well-written programs tend to exhibit good locality.
- These fundamental properties complement each other beautifully.
- They suggest an approach for organizing memory and storage systems
known as a memory hierarchy.
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width="50%"
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alt="Memory hierarchy"
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k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1.k more often than they access the data at level k+1.:::::{tab-set} ::::{tab-item} Cache
:::: ::::{tab-item} Cache hits
:::: ::::{tab-item} Cache misses
k+1 to a small subset (sometimes a singleton) of the block positions at level k. k+1 must be placed in block (i mod 4) at level k.k cache is large enough, but multiple data objects all map to the same level k block. :::: ::::{tab-item} Cache types
| Cache Type | What is cached | Where is it cached | Latency (cycles) | Managed By |
|---|---|---|---|---|
| Register | 4-6 byte words | CPU core | 0 | Compiler |
| TLB | Address translations | On-chip TLB | 0 | Hardware MMU |
| L1 cache | 64-byte blocks | On-chip L1 | 4 | Hardware |
| L2 cache | 64-byte blocks | On-chip L2 | 10 | Hardware |
| Virtual memory | 4-KB pages | Main memory | 100 | Hardware + OS |
| Buffer cache | Part of files | Main memory | 100 | OS |
| Disk cache | Disk sectors | Disk controller | 100,000 | Disk firmware |
| Network buffer cache | Part of files | Local disk | 10,000,000 | NFS client |
| Browser cache | Web pages | Local disk | 10,000,000 | Web browser |
| Web cache | Web pages | Remote server disks | 1,000,000,000 | Web proxy server |
::::
:::::{tab-set} ::::{tab-item} L2/L3
:::: ::::{tab-item} L1/L2/L3
::::
(misses / accesses) = 1 – hit rate miss rate is used instead of hit rate.
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## Write cache friendly code
- Make the common case go fast
- Focus on the inner loops of the core functions
- Minimize the misses in the inner loops
- Repeated references to variables are good (temporal locality)
- Stride-1 reference patterns are good (spatial locality)
- Key idea: our qualitative notion of locality is quantified through
our understanding of cache memories.
- Multiply N x N matrices
- Matrix elements are doubles (8 bytes)
- $O(N^{3})$ total operations
- N reads per source element
- N values summed per destination but may be able to hold in register
<script src="https://gist.github.com/linhbngo/d1e9336a82632c528ea797210ed0f553.js?file=mm.c"></script>
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sizes="95vw"
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<img
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width="50%"
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alt="Index increment directions in matrix multiplication"
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:::::{tab-set}
::::{tab-item} Case 1
~~~c
/* ijk */
for (i=0; i<n; i++) {
for (j=0; j<n; j++) {
sum = 0.0;
for (k=0; k<n; k++)
sum += a[i][k] * b[k][j];
c[i][j] = sum;
}
}
~~~
- Miss rate for inner loop iterations:
- Block size = 32 bytes (4 doubles)
- A = 8 / 32 = 0.25
- B = 1
- C = 0
- Average miss per iteration = 1.25
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https://developer.mozilla.org/en-US/docs/Learn/HTML/Multimedia_and_embedding/Responsive_images for info on defining 'sizes' for responsive images
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::::
::::{tab-item} Case 2
~~~c
/* kij */
for (k=0; k<n; k++) {
for (i=0; i<n; i++) {
r = a[i][k];
for (j=0; j<n; j++)
c[i][j] += r * b[k][j];
}
}
~~~
- Miss rate for inner loop iterations:
- Block size = 32 bytes (4 doubles)
- A = 0
- B = 8 / 32 = 0.25
- C = 8 / 32 = 0.25
- Average miss per iteration = 0.5
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See https://www.debugbear.com/blog/responsive-images#w-descriptors-and-the-sizes-attribute and
https://developer.mozilla.org/en-US/docs/Learn/HTML/Multimedia_and_embedding/Responsive_images for info on defining 'sizes' for responsive images
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<img
src="/assets/img/courses/csc231/05-memory/17.png"
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alt="Miss rate 2"
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::::
::::{tab-item} Case 3
~~~c
/* jki */
for (j=0; j<n; j++) {
for (k=0; k<n; k++) {
r = b[k][j];
for (i=0; i<n; i++)
c[i][j] += a[i][k] * r;
}
}
~~~
- Miss rate for inner loop iterations:
- Block size = 32 bytes (4 doubles)
- A = 1
- B = 0
- C = 1
- Average miss per iteration = 2
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https://developer.mozilla.org/en-US/docs/Learn/HTML/Multimedia_and_embedding/Responsive_images for info on defining 'sizes' for responsive images
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::::
- This is the cover of the book.
- Y-axis: Read throughput (read bandwidth)
- Number of bytes read from memory per second (MB/s)
- Memory mountain: Measured read throughput as a function of spatial and temporal locality.
- Compact way to characterize memory system performance.
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https://developer.mozilla.org/en-US/docs/Learn/HTML/Multimedia_and_embedding/Responsive_images for info on defining 'sizes' for responsive images
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<img
src="/assets/img/courses/csc231/05-memory/19.png"
width="50%"
height="auto"
alt="memory mountain"
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